1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a MOSFET and a method of fabricating the same.
2. Description of the Related Art
FIGS. 1 and 2 are cross-sectional views illustrating a method of fabricating a conventional MOSFET.
Referring to FIG. 1, an insulating layer and a gate conductive layer are sequentially formed on a semiconductor substrate 100. A mask pattern 130 is formed on the gate conductive layer to expose part of the surface of the gate conductive layer. An etch process is performed by using the mask pattern 130 as an etch mask to remove the exposed part of the gate conductive layer and insulating layer. As a result, a gate insulating layer pattern 110 and a gate conductive layer pattern 120 are formed. Also, part of the surface of the semiconductor substrate 100 is recessed by a predetermined thickness d and exposed. After the etch process is carried out, the mask pattern 130 is removed.
Referring to FIG. 2, an ion implantation buffer layer 130 is formed on the exposed surface of the semiconductor substrate 100 and the exposed surface of the gate conductive layer pattern 120. Next, an ion implantation process is implemented to form a lightly-doped drain (LDD) region 150 in a predetermined upper region of the semiconductor substrate 100. Then, gate spacers 140 are formed on sidewalls of the gate conductive layer pattern 120. Afterwards, another ion implantation process is implemented to form a heavily-doped region, i.e., a source/drain region 160. FIG. 3 is a diagram illustrating problems of the conventional MOSFET. In FIGS. 2 and 3, the same reference numerals represent the same elements.
As described above, the exposed surface of the semiconductor substrate 100 is recessed during the etch process for forming the gate conductive layer pattern 120. In addition, the exposed surface of the semiconductor substrate 100 may be recessed due to the etch process for removing the mask pattern (130 of FIG. 1) or a cleaning process to be performed after the ion implantation process. Because the exposed surface of the semiconductor substrate 100 is recessed, the LDD region 150, which is formed by the subsequent ion implantation process, cannot have a desired profile. That is, referring to FIG. 3, in a case where the exposed surface of the semiconductor substrate 100 is recessed, the LDD region (B) 150 moves to the left as indicated by the bigger arrow as compared with the LDD region (A) 150, which is formed in a case where the exposed surface of the semiconductor substrate 100 is not recessed. Also, the LDD region (B) 150 moves downward by a smaller length than the recessed thickness, as indicated by the smaller arrow. Although not shown in the drawing, it can be easily inferred that a similar phenomenon occurs also on the left side of the gate conductive layer pattern 120.
Accordingly, as the LDD region 150 is further extended toward the semiconductor substrate 100, properties of the MOSFET may be degraded. For example, the effective channel length may be shortened. As the effective channel length is reduced, a known short channel effect (SCE) is highly likely to occur. For another example, the resistance of the source/drain region may increase. While carriers come from the source region and pass through the channel region, the LDD region 150, and the drain region 160, resistances exist along the movement paths of the carriers and include the cumulative resistance Ra of the channel region, the spread resistance Rsp of the LDD region 150, the shunt resistance Rs of the drain region 160, and the contact resistance Rc of a contact region of the drain region 160. Among the resistances, the spread resistance Rsp of the LDD region 150 is affected by the profile of the LDD region 150. That is, because the LDD region 150 moves downward by the smaller length than the recessed thickness, the vertical sectional area of the LDD region 150 is reduced. Thus, the spread resistance Rsp of the LDD region 150 increases more. When the spread resistance Rsp of the LDD region 150 increases, electrical properties of the MOSFET are degraded.